The invention relates to a semiconductor component, in particular an EEPROM memory cell, having first and second doped zones of a first conduction type disposed in a semiconductor substrate of a second conduction type, and a channel zone in the semiconductor substrate between the two doped zones. The invention also relates to a method for producing a semiconductor component.
EEPROM (Electrically Erasable Programmable Read-Only Memories) cells play an ever more important role among types of memory. In the case of chip card applications, for instance, memory blocks of the FLOTOX (Floating Gate Tunnel Oxide) cell type are used, which are integrated into a microcontroller environment (embedded memories). There is a demand for ever smaller cells. A limiting factor is the shrinkability of a tunnel window with an associated electrical connection zone (buried channel). That limit is determined primarily by the properties of the device, as is described below and in German Published, Non-Prosecuted Patent Application DE 196 14 010 A1, owned by the assignee of the instant application.
The disadvantages of such prior art components and methods are that they require a great deal of space and do not have high electrical reliability, as is described in more detail below in the description of FIGS. 1-4.
It is accordingly an object of the invention to provide a semiconductor component with compensation implantation and a production method, which overcome the hereinafore-mentioned disadvantages of the heretofore-known products and methods of this general type and which provide an EPROM that does not require very much space and has high electrical reliability.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor component, comprising a semiconductor substrate of a second conduction type; first and second doped zones of a first conduction type disposed in the semiconductor substrate, the first doped zone having a surface and a peripheral region; a channel zone disposed between the first and second doped zones in the semiconductor substrate, the channel zone having a surface; a tunnel dielectric partly covering the surface of the first doped zone and defining a given region of the first doped zone disposed under the tunnel dielectric; a gate dielectric covering the surface of the channel zone and the peripheral region of the first doped zone; and a gate electrode on the tunnel dielectric and on the gate dielectric; the peripheral region having a higher effective doping than the given region.
In accordance with another feature of the invention, the given region of the first doped zone contains one dopant of the first conduction type and one dopant of the second conduction type.
In accordance with a further feature of the invention, the dopant of the first conduction type is present in the peripheral region, and the dopant of the second conduction type has a concentration very much less than in the given region below the tunnel dielectric.
In accordance with an added feature of the invention, the dopant of the first conduction type is phosphorous and the dopant of the second conduction type is boron or gallium.
With the objects of the invention in view there is also provided a method for producing a semiconductor component, which comprises producing first and second doped zones of a first conduction type and a peripheral region of the first doped zone in a semiconductor substrate of a second conduction type; producing a channel zone between the first and second doped zones in the semiconductor substrate; producing a connection for the first doped zone; creating a gate dielectric on the semiconductor substrate covering a surface of the channel zone and the peripheral region of the first doped zone; applying a mask on the gate dielectric with an opening in a region of the mask for later application of a tunnel dielectric; producing a doped zone of a first conduction type under the opening by an implantation through the gate dielectric; performing a compensation implantation with a dopant of the second conduction type providing a lowered effective dopant concentration of the first conduction type in a region near a surface below the opening, after the two implantations; removing the gate dielectric inside the opening in the mask; removing the mask and baring a surface of the semiconductor substrate; creating a tunnel dielectric on the bared semiconductor substrate surface while partly covering a surface of the first doped zone with the tunnel dielectric; and producing a gate electrode on the tunnel dielectric and on an adjacent portion of the gate dielectric.
In accordance with another mode of the invention, there is provided a production method which comprises implanting the first doped zone with phosphorous.
In accordance with a further mode of the invention, there is provided a production method which comprises carrying out the compensation implantation with gallium.
In accordance with an added mode of the invention, there is provided a production method which comprises modifying lateral dimensions of the mask prior to the compensation implantation.
In accordance with an additional mode of the invention, there is provided a production method which comprises forming the mask of photoresist swelling prior to the compensation implantation.
In accordance with yet another mode of the invention, there is provided a production method which comprises carrying out the compensation implantation with boron.
In accordance with yet a further mode of the invention, there is provided a production method which comprises carrying out the compensation implantation prior to the implantation with the dopant of the first conduction type.
In accordance with a concomitant mode of the invention, there is provided a production method which comprises carrying out the compensation implantation with a lower dose than the implantation with the dopant of the first conduction type.
In the invention, the level of the potential barrier is adjusted through the use of the lateral dopant profile. The following discovery is utilized in this case: the weaker the effective doping in the buried channel, the higher the potential at the boundary surface (that is, the hole potential is lower). A high potential barrier can be attained through the use of a high potential in the buried channel and a low potential in the peripheral region, or in other words under the gate dielectric or at the boundary between the gate dielectric and the tunnel dielectric, or again through the use of weak doping in the buried channel and higher doping in the peripheral region. The lateral dopant profile in the vicinity of the semiconductor substrate surface accordingly has at least a local maximum in the peripheral region. The effective concentration of n-dopants is greater in the peripheral region than in a region below the tunnel window.
This kind of dopant profile can be attained since in addition to the implantation of the buried channel, a compensation implantation with dopant atoms of the opposite conduction type is performed, in which the lateral out- diffusion is less than in the buried channel implantation. The same implantation mask is used for this purpose, optionally modified.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor component with compensation implantation and a production method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.